Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern

ABSTRACT

A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of deforming a resistpattern to be used for forming a semiconductor device, and moreparticularly to a method of improving the accuracy in the quantity ofdeformation of an original resist pattern or improving a highly accuratecontrol to a pattern shape of a reflow-deformed resist pattern.

[0003] 2. Description of the Related Art

[0004] A conventional well known method of deforming the original resistpattern is a re-flow process by heating the original resist pattern. Aquantity of deformation of the resist pattern or a difference in size ofthe deformed resist pattern from the original resist pattern isrelatively small, for example, in the range of 0.5 micrometers to 3micrometers.

[0005] Another conventional well known method of deforming the originalresist pattern is to dip the original resist pattern into chemicals orexpose the original resist pattern to a steam containing chemicals sothat the chemicals osmose into the original resist pattern, whereby theoriginal resist pattern is dissolved and deformed. A quantity ofdeformation of the resist pattern or a difference in size of thedeformed resist pattern from the original resist pattern is relativelylarge, for example, in the range of 5 micrometers to 20 micrometers.

[0006] A high accuracy in the quantity of deformation of the resistpattern is desired. In order to obtain the high accuracy in quantity ofthe deformation, a highly accurate control to the quantity ofdeformation of the resist pattern is essential.

[0007] A conventional method of forming a thin film transistor utilizesthe original resist pattern and the deformed resist pattern. FIG. 1A isa fragmentary plan view of a thin film transistor of a first stepinvolved in conventional sequential fabrication processes. FIG. 1B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 1A, taken along a D-D′ line. FIG. 2A is a fragmentary planview of a thin film transistor of a second step involved in conventionalsequential fabrication processes. FIG. 2B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 2A,taken along a D-D′ line. FIG. 3A is a fragmentary plan view of a thinfilm transistor of a third step involved in conventional sequentialfabrication processes. FIG. 3B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 3A, taken along aD-D′ line. FIG. 4A is a fragmentary plan view of a thin film transistorof a fourth step involved in conventional sequential fabricationprocesses. FIG. 4B is a fragmentary cross sectional elevation view of athin film transistor shown in FIG. 4A, taken along a D-D′ line. A thinfilm transistor is formed over an insulating substrate 301.

[0008] With reference to FIGS. 1A and 1B, a metal layer is formed on atop surface of an insulating substrate 301. The metal layer is thenpatterned to form a gate electrode 302. A gate insulating film 303 isformed over the top surface of the insulating substrate 301 and over thegate electrode 302. An amorphous silicon film 304 is formed over thegate insulating film 303. An n+-type amorphous silicon film 305 isformed over the amorphous silicon film 304. A metal layer 306 is formedover the n+-type amorphous silicon film 305.

[0009] Thick resist masks 318 and thin resist masks 328 are selectivelyformed over the metal layer 306. The thick resist masks 318 are adjacentto a channel region 315. The thick resist masks 318 separates the thinresist masks 328 from the channel region 315. The thick resist masks 318have a thickness of about 3 micrometers. The thin resist masks 328 havea thickness of about 0.2-0.7 micrometers. Each pair of the thick resistmask 318 and the thin resist mask 328 comprises a unitary-formed resistmask which varies in thickness.

[0010] With reference to FIGS. 2A and 2B, a first anisotropic etchingprocess is carried out by using the thick and thin resist masks 318 and328 for selectively etching the metal layer 306 and the n+-typeamorphous silicon film 305, whereby the remaining parts of the n+-typeamorphous silicon film 305 become a source side ohmic contact layer 310and a drain side ohmic contact layer 311, and further the remainingparts of the metal layer 306 become a source electrode 313 and a drainelectrode 314.

[0011] A plasma ashing process is carried out in the presence of O₂plasma for reducing the thickness of the resist masks, whereby the thinresist masks 328 are removed, while the thick resist masks 318 remainwith a reduced thickness. These thickness-reduced resist masks 318 willhereinafter be referred to as residual resist masks 338. The residualresist masks 338 are adjacent to the channel region 315. These residualresist masks 338 provide the original resist patterns.

[0012] With reference to FIGS. 3A and 3B, the residual resist masks 338are exposed to a steam for 1-3 minutes, wherein the steam contains anorganic solvent, whereby the organic solvent gradually osmose into theresidual resist masks 338 as the original resist patterns, so that theoriginal resist pattern is dissolved and re-flowed, resulting in areflow-deformed resist pattern 348 being formed. The reflow-deformedresist pattern 348 extends to the channel region 315 and outside regionsof the residual resist masks 338 as the original resist patterns.

[0013] In the re-flow process, the residual resist masks 338 as theoriginal resist patterns are inwardly re-flowed toward the channelregion 315 and the re-flowed residual resist masks 338 come togetherover the channel region 315. An interconnection 302′ connected to thegate electrode 302 extends in a parallel direction to the line D-D′.This interconnection 302′ forms a step-like barrier wall 317-a to stopthe reflow of the re-flowed residual resist masks 338, wherein thestep-like barrier wall 317-a extends in the parallel direction to theline D-D′. A further step-like barrier wall 317-b is present, whichextends in a perpendicular direction to the D-D′ line.

[0014] For this reason, the reflow of the residual resist masks 338 isstopped but only in two directions by the step-like barrier walls 317-aand 371 b. The reflow of the residual resist masks 338 is free and notlimited in the remaining directions. It is difficult to control thereflow of the residual resist masks 338 in the remaining directions dueto the absence of any re-flow restrictor such as the step-like barrierwalls 317-a and 371 b. This means it difficult to control the patternshape of the reflow-deformed resist mask 348.

[0015] With reference to FIGS. 4A and 4B, a second anisotropic etchingprocess is carried out by use of the reflow-deformed resist mask 348 andthe source and drain electrodes 313 and 314 as masks for selectivelyetching the amorphous silicon film 304, whereby the remaining part ofthe amorphous silicon film 304 becomes an island layer 324. A patternshape of the island layer 324 is defined by the reflow-deformed resistmask 348 in combination with additional masks of the source and drainelectrodes 313 and 314. The used reflow-deformed resist mask 348 isremoved. As a result, a reverse staggered thin film transistor isformed.

[0016] As described above, the pattern shape of the island layer 324 isdefined by the reflow-deformed resist mask 348 in combination withadditional masks of the source and drain electrodes 313 and 314.Further, it is difficult to control the reflow of the residual resistmasks 338 in the remaining directions due to the absence of any re-flowrestrictor such as the step-like barrier walls 317-a and 371 b. It isdifficult to control the pattern shape of the reflow-deformed resistmask 348. This means it difficult to control the pattern shape of theisland layer 324. The island layer 324 of amorphous silicon underliesthe source and drain sides ohmic contact layers 310 and 311. The islandlayer 324 is thus electrically connected to the source and drainelectrodes 313 and 314. A parasitic capacitance between the gateelectrode 302 and the source and drain electrodes 313 and 314 depends onthe pattern shape of the island layer 324. In order to precisely controlthe parasitic capacitance, it is essential to control the pattern shapeof the reflow-deformed resist mask 348 or to control the pattern shapeof the island layer 324.

[0017] In the above circumstances, the development of a novel improvinga highly accurate control to a pattern shape of a reflow-deformed resistpattern free from the above problems is desirable.

SUMMARY OF THE INVENTION

[0018] Accordingly, it is an object of the present invention to providea novel method of deforming a resist pattern to be used for forming asemiconductor device free from the above problems.

[0019] It is a further object of the present invention to provide anovel method of improving the accuracy in the quantity of deformation ofan original resist pattern.

[0020] It is a still further object of the present invention to providea novel method improving a highly accurate control to a pattern shape ofa reflow-deformed resist pattern.

[0021] It is yet a further object of the present invention to provide anovel method of patterning a layer by use of a deformed resist patternfrom an original resist pattern.

[0022] It is yet a further object of the present invention to provide anovel method of forming a semiconductor device by use of both originaland deformed resist patterns in different processes.

[0023] It is a further primary object of the present invention toprovide a semiconductor device formed by utilizing a novel method ofdeforming a resist pattern.

[0024] It is another object of the present invention to provide asemiconductor device formed by utilizing a novel method of improving theaccuracy in the quantity of deformation of an original resist pattern.

[0025] It is still another object of the present invention to provide asemiconductor device formed by utilizing a novel method improving ahighly accurate control to a pattern shape of a reflow-deformed resistpattern.

[0026] It is yet another object of the present invention to provide asemiconductor device formed by utilizing a novel method of patterning alayer by use of a deformed resist pattern from an original resistpattern.

[0027] It is further another object of the present invention to providea semiconductor device formed by utilizing a novel method of forming asemiconductor device by use of both original and deformed resistpatterns in different processes.

[0028] The present invention provides a method of deforming a patterncomprising the steps of: forming, over a substrate, a layered-structurewith an upper surface including at least one selected region and atleast a re-flow stopper groove, wherein the re-flow stopper grooveextends outside the selected region and separate from the selectedregion; selectively forming at least one pattern on the selected region;and causing a re-flow of the pattern, wherein a part of an outwardlyre-flowed pattern is flowed into the re-flow stopper groove, and then anoutward re-flow of the pattern is restricted by the re-flow stoppergroove extending outside of the pattern, thereby to form a deformedpattern with at least an outside edge part defined by an outside edge ofthe re-flow stopper groove.

[0029] The above and other objects, features and advantages of thepresent invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Preferred embodiments according to the present invention will bedescribed in detail with reference to the accompanying drawings.

[0031]FIG. 1A is a fragmentary plan view of a thin film transistor of afirst step involved in conventional sequential fabrication processes.

[0032]FIG. 1B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 1A, taken along a D-D′ line.

[0033]FIG. 2A is a fragmentary plan view of a thin film transistor of asecond step involved in conventional sequential fabrication processes.

[0034]FIG. 2B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 2A, taken along a D-D′ line.

[0035]FIG. 3A is a fragmentary plan view of a thin film transistor of athird step involved in conventional sequential fabrication processes.

[0036]FIG. 3B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 3A, taken along a D-D′ line.

[0037]FIG. 4A is a fragmentary plan view of a thin film transistor of afourth step involved in conventional sequential fabrication processes.

[0038]FIG. 4B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 4A, taken along a D-D′ line.

[0039]FIG. 5A is a fragmentary plan view of a thin film transistor of afirst step involved in novel sequential fabrication processes in a firstembodiment in accordance with the present invention.

[0040]FIG. 5B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 5A, taken along an A-A′ line.

[0041]FIG. 6A is a fragmentary plan view of a thin film transistor of asecond step involved in novel sequential fabrication processes in afirst embodiment in accordance with the present invention.

[0042]FIG. 6B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 6A, taken along an A-A′ line.

[0043]FIG. 7A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a firstembodiment in accordance with the present invention.

[0044]FIG. 7B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 7A, taken along an A-A′ line.

[0045]FIG. 8A is a fragmentary plan view of a thin film transistor of afourth step involved in novel sequential fabrication processes in afirst embodiment in accordance with the present invention.

[0046]FIG. 8B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 8A, taken along an A-A′ line.

[0047]FIG. 9A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a firstmodification to the first embodiment in accordance with the presentinvention.

[0048]FIG. 9B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 9A, taken along an A-A′ line.

[0049]FIG. 10A is a fragmentary plan view of a thin film transistor of afirst step involved in novel sequential fabrication processes in asecond embodiment in accordance with the present invention.

[0050]FIG. 10B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 10A, taken along an A-A′ line.

[0051]FIG. 11A is a fragmentary plan view of a thin film transistor of asecond step involved in novel sequential fabrication processes in asecond embodiment in accordance with the present invention.

[0052]FIG. 11B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 11A, taken along an A-A′ line.

[0053]FIG. 12A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in asecond embodiment in accordance with the present invention.

[0054]FIG. 12B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 12A, taken along an A-A′ line.

[0055]FIG. 13A is a fragmentary plan view of a thin film transistor of afourth step involved in novel sequential fabrication processes in asecond embodiment in accordance with the present invention.

[0056]FIG. 13B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 13A, taken along an A-A′ line.

[0057]FIG. 14A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a firstmodification to the second embodiment in accordance with the presentinvention.

[0058]FIG. 14B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 14A, taken along an A-A′ line.

[0059]FIG. 15A is a fragmentary plan view of a thin film transistor of afirst step involved in novel sequential fabrication processes in a thirdembodiment in accordance with the present invention.

[0060]FIG. 15B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 15A, taken along an A-A′ line.

[0061]FIG. 16A is a fragmentary plan view of a thin film transistor of asecond step involved in novel sequential fabrication processes in athird embodiment in accordance with the present invention.

[0062]FIG. 16B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 16A, taken along an A-A′ line.

[0063]FIG. 17A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a thirdembodiment in accordance with the present invention.

[0064]FIG. 17B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 17A, taken along a B-B′ line.

[0065]FIG. 18A is a fragmentary plan view of a thin film transistor of afirst step involved in novel sequential fabrication processes in afourth embodiment in accordance with the present invention.

[0066]FIG. 18B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 18A, taken along a C-C′ line.

[0067]FIG. 19A is a fragmentary plan view of a thin film transistor of asecond step involved in novel sequential fabrication processes in afourth embodiment in accordance with the present invention.

[0068]FIG. 19B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 19A, taken along a C-C′ line.

[0069]FIG. 20A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in afourth embodiment in accordance with the present invention.

[0070]FIG. 20B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 20A, taken along a C-C′ line.

[0071]FIG. 21A is a fragmentary plan view of a thin film transistor of afirst step involved in novel sequential fabrication processes in a fifthembodiment in accordance with the present invention.

[0072]FIG. 21B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 21A, taken along an E-E′ line.

[0073]FIG. 22A is a fragmentary plan view of a thin film transistor of asecond step involved in novel sequential fabrication processes in afifth embodiment in accordance with the present invention.

[0074]FIG. 22B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 22A, taken along an E-E′ line.

[0075]FIG. 23A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a fifthembodiment in accordance with the present invention.

[0076]FIG. 23B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 23A, taken along an E-E′ line.

[0077]FIG. 24A is a fragmentary plan view of a thin film transistor of afourth step involved in novel sequential fabrication processes in afifth embodiment in accordance with the present invention.

[0078]FIG. 24B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 24A, taken along an E-E′ line.

[0079]FIG. 25A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a firstmodification to the fifth embodiment in accordance with the presentinvention.

[0080]FIG. 25B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 25A, taken along an F-F′ line.

[0081]FIG. 26A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in asecond modification to the fifth embodiment in accordance with thepresent invention.

[0082]FIG. 26B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 26A, taken along an F-F′ line.

[0083]FIG. 27A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a thirdmodification to the fifth embodiment in accordance with the presentinvention.

[0084]FIG. 27B is a fragmentary cross sectional elevation view of a thinfilm transistor shown in FIG. 27A, taken along an F-F′ line.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0085] A first aspect of the present invention is a method of deforminga pattern. The method comprises the steps of: forming, over a substrate,a layered-structure with an upper surface including at least oneselected region and at least a re-flow stopper groove, wherein there-flow stopper groove extends outside the selected region and separatefrom the selected region; selectively forming at least one pattern onthe selected region; and causing a re-flow of the pattern, wherein apart of an outwardly re-flowed pattern is flowed into the re-flowstopper groove, and then an outward reflow of the pattern is restrictedby the re-flow stopper groove extending outside of the pattern, therebyto form a deformed pattern with at least an outside edge part defined byan outside edge of the re-flow stopper groove.

[0086] It is preferable that the re-flow stopper groove excludes achannel region, and parts of the outwardly re-flowed pattern are flowedinto both the re-flow stopper groove and the channel region.

[0087] It is further preferable that the re-flow stopper groove isseparate from the channel region.

[0088] It is further more preferable that the re-flow stopper groove ispositioned indirectly over a gap between a gate electrode and at least adummy gate electrode.

[0089] It is also preferable that the re-flow stopper groove comprises arecessed trench groove formed in the layered-structure.

[0090] It is also preferable that the re-flow stopper groove comprises afirst gap between a source electrode and a dummy source electrode and asecond gap between a drain electrode and a dummy drain electrode.

[0091] It is also preferable that the re-flow stopper groove is adjacentto the channel region.

[0092] It is further preferable that the re-flow stopper groove ispositioned indirectly over a gap between a gate electrode and at least adummy gate electrode.

[0093] It is further preferable that the re-flow stopper groove isdefined by both a side wall of an extending layer from one of source anddrain electrodes and a stepped portion of the channel region, where thestepped portion is positioned indirectly over an edge of a gateelectrode.

[0094] It is also preferable that the re-flow stopper groove includes achannel region, and a part of the outwardly re-flowed pattern is flowedinto the re-flow stopper groove.

[0095] It is further preferable that the re-flow stopper groove and thechannel region are in forms of annular shape, and an outside peripheraledge of the re-flow stopper groove encompasses an outside peripheraledge of the channel region, and the outside peripheral edge of there-flow stopper groove is defined by stepped portions of source anddrain electrodes, where the stepped portions of the source and drainelectrodes are positioned indirectly over a stepped portion of a gateelectrode, and where the stepped portion of the gate electrode extendsin a form of annular shape and defines a depressed region of the gateelectrode.

[0096] It is also preferable that the re-flow stopper groove is includedin a channel region which extends outside the selected region, and apart of the outwardly re-flowed pattern is flowed into the channelregion.

[0097] It is further preferable that the re-flow stopper groove ispositioned indirectly over a groove of a gate electrode.

[0098] It is also preferable that the re-flow stopper groove justoverlaps a channel region which extends outside the selected region, anda part of the outwardly re-flowed pattern is flowed into the re-flowstopper groove.

[0099] It is also preferable that the re-flow stopper groove and thechannel region are an annular shaped region which is defined by anisland-shaped electrode and an annular-shaped electrode which surroundsthe island-shaped electrode completely.

[0100] It is also preferable that the re-flow stopper groove surroundsthe selected region completely.

[0101] It is also preferable that the re-flow stopper groove surroundsthe selected region incompletely.

[0102] It is also preferable that the selected region comprises a set ofplural selected regions separate from each other and adjacent to eachother, and the re-flow stopper groove surrounds the set of pluralselected regions completely.

[0103] It is also preferable that the selected region comprises a set ofplural selected regions separate from each other and adjacent to eachother, and the re-flow stopper groove surrounds the set of pluralselected regions incompletely.

[0104] It is also preferable that the pattern is a pattern containing anorganic material.

[0105] It is further preferable that the pattern is a resist pattern.

[0106] A second aspect of the present invention is a method of forming are-flowed pattern over a layered-structure. The method comprises thesteps of: forming an original resist pattern over a layered-structurewith an upper surface including at least one selected region and atleast a re-flow stopper groove wherein extends outside the selectedregion and separate from the selected region, and the original resistpattern comprising a thicker portion and a thinner portion, and thethicker portion extending on a selected region, patterning alayered-structure by use of the original resist pattern; removing thethinner portion and reducing a thickness of the thicker portion to forma residual resist pattern unchanged in pattern shape from the thickerportion; and causing a re-flow of the residual pattern, wherein a partof an outwardly re-flowed pattern is flowed into the re-flow stoppergroove, and then an outward re-flow of the pattern is restricted by there-flow stopper groove extending outside of the pattern, thereby to forma deformed pattern with at least an outside edge part defined by anoutside edge of the re-flow stopper groove.

[0107] A third aspect of the present invention is a method of patterninga layered-structure. The method comprises the steps of: forming anoriginal resist pattern over a layered-structure with an upper surfaceincluding at least one selected region and at least a re-flow stoppergroove wherein extends outside the selected region and separate from theselected region, and the original resist pattern comprising a thickerportion and a thinner portion, and the thicker portion extending on aselected region, patterning a layered-structure by use of the originalresist pattern; removing the thinner portion and reducing a thickness ofthe thicker portion to form a residual resist pattern unchanged inpattern shape from the thicker portion; and causing a re-flow of theresidual pattern, wherein a part of an outwardly re-flowed pattern isflowed into the re-flow stopper groove, and then an outward re-flow ofthe pattern is restricted by the re-flow stopper groove extendingoutside of the pattern, thereby to form a deformed pattern with at leastan outside edge part defined by an outside edge of the re-flow stoppergroove; and patterning the layered-structure by use of the deformedpattern.

[0108] A fourth aspect of the present invention is a semiconductordevice including gate, source and drain electrodes, a layered structureover a substrate, and the layered structure has a surface which furtherhas at least a groove, wherein the groove extends outside at least aselected region on the layered-structure, and the selected region beingadjacent to a channel region, and the groove extends outside of the gateelectrode, and the groove is separate by a gap from the gate electrode.

[0109] It is preferable that the groove surrounds the gate electrodeincompletely.

[0110] It is also preferable that the groove surrounds the gateelectrode completely.

[0111] It is further preferable that the groove extends in an annularform.

[0112] A fifth aspect of the present invention is a semiconductor deviceincluding gate, source and drain electrodes, a layered structure over asubstrate, and at least a groove formed in the layered structure,wherein the groove extends outside at least a selected region on thelayered-structure, and the selected region being adjacent to a channelregion, and the groove extends outside of the gate electrode, and thegroove is separate by a gap from the gate electrode.

[0113] It is also preferable that the groove surrounds the gateelectrode incompletely.

[0114] It is also preferable that the groove surrounds the gateelectrode completely.

[0115] It is also preferable that the groove extends in an annular form.

[0116] A sixth aspect of the present invention is a semiconductor deviceincluding a gate electrode and a layered-structure, wherein the gateelectrode has at least a step, and an upper surface of thelayered-structure also has at least a step which is positioned over thestep of the gate electrode.

[0117] It is also preferable that the gate has a thickness-reducedregion bounded by the step.

[0118] A seventh aspect of the present invention is a semiconductordevice including a gate electrode structure which further comprises atleast a gate electrode and at least a dummy gate electrode, wherein thedummy gate electrode is separate by a gap from the gate electrode andpositioned outside of the gate electrode.

[0119] It is also preferable that the dummy gate electrode surrounds thegate electrode incompletely.

[0120] It is also preferable that the dummy gate electrode surrounds thegate electrode completely.

[0121] It is also preferable that the dummy gate electrode extends in anannular form.

[0122] It is also preferable that the dummy gate electrode extendsadjacent to and parallel to a flat side of the gate electrode.

[0123] It is also preferable that the semiconductor device furtherincludes a multi-layer structure comprising plural laminated layerswhich extend over the gate electrode structure, and surfaces of theplural laminated layers have grooves which are positioned over the gap.

[0124] An eighth aspect of the present invention is a semiconductordevice including gate, source and drain electrodes, a layered structureover a substrate, and at least a groove in the layered structure,wherein the groove extends outside at least a selected region on thelayered-structure, and the selected region being adjacent to a channelregion, and the groove extends outside of the gate electrode, and thegroove is separate by a gap from the gate electrode, and wherein atleast a part of the source and drain electrodes is present in thegroove.

[0125] It is also preferable that the groove surrounds the gateelectrode incompletely.

[0126] It is also preferable that the groove surrounds the gateelectrode completely.

[0127] It is also preferable that the groove extends in an annular form.

[0128] It is also preferable that the groove extends adjacent to andparallel to a flat side of the gate electrode.

[0129] A ninth aspect of the present invention is a semiconductor deviceincluding gate, source and drain electrodes, dummy source and drainelectrodes, a layered structure over a substrate, and at least a groove,wherein the dummy source and drain electrodes are positioned outside thesource and drain electrodes, and the groove separates the source anddrain electrodes from the dummy source and drain electrodes, and whereinthe groove extends outside at least a selected region on thelayered-structure, and the selected region being adjacent to a channelregion, and the groove extends outside of the gate electrode in planview, and the groove is separate from the gate electrode in plan view.

[0130] It is also preferable that the groove surrounds the gateelectrode incompletely.

[0131] It is also preferable that the groove surrounds the gateelectrode completely.

[0132] It is also preferable that the groove extends in an annular form.

[0133] It is also preferable that the groove extends adjacent to andparallel to a flat side of the gate electrode.

[0134] A tenth aspect of the present invention is a semiconductor deviceincluding gate, source and drain electrodes, a channel region, and atleast a groove, wherein first one of the source and drain electrodesincludes an island portion, and second one of the source and drainelectrodes includes a surrounding portion which surrounds the channelregion, and the channel region further surrounds the island portion, andthe surrounding portion is separate by the channel region from theisland portion, and wherein the groove includes the channel region.

[0135] It is also preferable that the surrounding portion surrounds theisland portion incompletely.

[0136] It is also preferable that the groove further includes anadditional groove which extends adjacent to an opening side of thesurrounding portion.

[0137] It is also preferable to further comprise a dummy gate electrodeseparate by a gap from the gate electrode, wherein the additional grooveis positioned over the gap.

[0138] It is also preferable that the first one further includes aconnecting portion, and an additional extending portion which extendsadjacent to an opening side of the surrounding portion and which facesto the opening side, and the additional extending portion is connectedthrough the connecting portion to the island portion.

[0139] It is also preferable that the connecting portion has a step-likewall.

[0140] It is also preferable that the surrounding portion surrounds theisland portion completely.

[0141] It is also preferable that the groove extends in an annular form.

[0142] An eleventh aspect of the present invention is a semiconductordevice including a layered-structure over a substrate, wherein an uppersurface of the substrate has at least a groove, and an upper surface ofthe layered-structure also has at least a groove which is positionedover the groove of the substrate, and wherein the groove of thesubstrate selectively extends adjacent to a channel region.

[0143] It is also preferable that the groove of the substrate extendsaround the channel region in plan view.

[0144] It is also preferable that the groove of the substrate surroundscompletely.

[0145] It is also preferable that the groove of the substrate surroundsincompletely.

[0146] A twelfth aspect of the present invention is a semiconductordevice including a layered-structure over a substrate, wherein an uppersurface of the substrate has at least a level-down region, and an uppersurface of the layered-structure also has at least a groove whichextends over the level-down region of the substrate, and wherein thelevel-down region of the substrate selectively extends including achannel region in plan view.

First Embodiment

[0147] A first embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 5A is afragmentary plan view of a thin film transistor of a first step involvedin novel sequential fabrication processes in a first embodiment inaccordance with the present invention. FIG. 5B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 5A,taken along an A-A′ line. FIG. 6A is a fragmentary plan view of a thinfilm transistor of a second step involved in novel sequentialfabrication processes in a first embodiment in accordance with thepresent invention. FIG. 6B is a fragmentary cross sectional elevationview of a thin film transistor shown in FIG. 6A, taken along an A-A′line. FIG. 7A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a firstembodiment in accordance with the present invention. FIG. 7B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 7A, taken along an A-A′ line. FIG. 8A is a fragmentaryplan view of a thin film transistor of a fourth step involved in novelsequential fabrication processes in a first embodiment in accordancewith the present invention. FIG. 8B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 8A, taken alongan A-A′ line. A thin film transistor is formed over an insulatingsubstrate 1.

[0148] With reference to FIGS. 5A and 5B, a bottom conductive film isformed over a top surface of the insulating substrate 1. The bottomconductive film is patterned to form a gate electrode interconnection 2and a dummy gate electrode 12. The gate electrode interconnection 2 hasa gate electrode 2 which has a rectangle shape in plan view. The gateelectrode 2 extends from the gate electrode interconnection 2 in adirection perpendicular to a longitudinal direction of the gateelectrode interconnection 2. The dummy gate electrode 12 is generallyU-shaped, so that the dummy gate electrode 12 surrounds therectangle-shaped gate electrode 2. The dummy gate electrode 12 isseparate from the gate electrode 2 and from the gate electrodeinterconnection 2. One side of the gate electrode 2 is bounded with thegate electrode interconnection 2. The dummy gate electrode 12 extendsalong the remaining three sides of the gate electrode 2. An U-shaped gapis defined between inside edges of the dummy gate electrode 12 and theremaining three sides of the gate electrode 2. The U-shaped gap has anuniform width and is formed between the gate electrode 2 and the dummygate electrode 12.

[0149] A gate insulating film 3 having a thickness of 3500 nanometers isformed over the insulating substrate 1 and the gate electrodeinterconnection 2, the gate electrode 2 and the dummy gate electrode 12,wherein the gate insulating film 3 fills the U-shaped gap between insideedges of the dummy gate electrode 12 and the remaining three sides ofthe gate electrode 2. An upper surface of the gate insulating film 3 hasa groove which extends in a form of generally U-shape in plan view. Thegroove extends over the U-shaped gap between the gate electrode 2 andthe dummy gate electrode 12. The groove in the upper surface of the gateinsulating film 3 is thus formed by the U-shaped gap between the gateelectrode 2 and the dummy gate electrode 12.

[0150] An amorphous silicon film 4 having a thickness of 200 nanometersis formed over the upper surface of the gate insulating film 3. An uppersurface of the amorphous silicon film 4 also has a groove which extendsin a form of generally U-shape in plan view. The groove extends over theU-shaped groove in the upper surface of the gate insulating film 3.

[0151] An n+-type amorphous silicon film 5 having a thickness of 50nanometers is formed over the upper surface of the amorphous siliconfilm 4. An upper surface of the n+-type amorphous silicon film 5 alsohas a groove which extends in a form of generally U-shape in plan view.The groove extends over the U-shaped groove in the upper surface of theamorphous silicon film 4.

[0152] A top conductive film 6 is formed over the upper surface of then+-type amorphous silicon film 5. An upper surface of the top conductivefilm 6 also has a reflow stopper groove 7 which extends in a form ofgenerally U-shape in plan view. The reflow stopper groove 7 extends overthe U-shaped groove in the upper surface of the n+-type amorphoussilicon film 5. The reflow stopper groove 7 is positioned indirectlyover the U-shaped gap between the gate electrode 2 and the dummy gateelectrode 12.

[0153] A resist mask 8 is selectively formed over the upper surface ofthe top conductive film 6 by use of a lithography technique. The resistmask 8 comprises a thick resist mask 18 and a thin resist mask 28. Thethick resist mask 18 is positioned in selected regions adjacent to achannel region 15 which has a rectangle shape. The selected regions alsohave rectangle shape regions along opposite outsides of the rectangleshape channel region 15. The thick resist mask 18 may have a thicknessof about 3 micrometers. The thin resist mask 28 may have a thickness ofabout 0.2-0.7 micrometers.

[0154] With reference to FIGS. 6A and 6B, a first etching process iscarried out by use of the thick and thin resist masks 18 and 28 forselectively etching the top conductive film 6 and the n+-type amorphoussilicon film 5. The top conductive film 6 may comprise a metal film. Thetop conductive film 6 may selectively be etched by a wet etching processto form source and drain electrodes 13 and 14. The n+-type amorphoussilicon film 5 may also selectively be etched by a dry etching processunder a pressure of 10 Pa, at a power of 1000W for 60 seconds, whereinsource gas flow rate ratios of SF₆/HCl/He are 100/100/150 sccm to formohmic contact layers 10 and 11 which underlie the source and drainelectrodes 13 and 14, thereby making ohmic contacts between theamorphous silicon film 4 and the source and drain electrodes 13 and 14.

[0155] Subsequently, a plasma ashing process is carried out in thepresence of plasma atmosphere with oxygen flow rate at 400 sccm under apressure of 20 Pa, and an RF power of 1000 W for 120 seconds. Thisplasma ashing process reduces the thickness of the resist mask 8,whereby the thin resist mask 28 is removed whilst the thick resist mask18 is reduced in thickness, whereby the thickness-reduced resist mask 18becomes a residual resist mask 38 which extends on the selected regionsadjacent to the channel region 15.

[0156] With reference to FIGS. 7A and 7B, the residual resist mask 38 isthen exposed to a steam of a solution which contains an organic solventsuch as ethylcellsolveacetate (ECA) or N-methyl-2-pyrolidinone at 27° C.for 1-3 minutes. This exposure process causes the organic solvent toosmose into the residual resist mask 38, whereby the residual resistmask 38 is dissolved and re-flowed, and the residual resist mask 38becomes a reflow-deformed resist mask 48.

[0157] A part of the re-flowed resist mask 48 is dropped into thechannel region 15 and other parts of the re-flowed resist mask 48 aredropped into the reflow stopper groove 7 which extends in a form of thegenerally U-shape and positioned indirectly over the U-shaped gapbetween the gate electrode 2 and the dummy gate electrode 12. An inwardreflow of the resist mask 48 is dropped into the channel region 15 and afurther inward reflow of the resist mask 48 is restricted by the channelregion 15. An outward reflow of the resist mask 48 is omnidirectional.The outward reflow of the resist mask 48 in one direction toward astep-like barrier wall 17 which extends indirectly over an edge of thegate electrode interconnection 2 is stopped or restricted by thestep-like barrier wall 17. The remaining outward reflow of the resistmask 48 in the remaining three directions toward the reflow stoppergroove 7 is dropped into the reflow stopper groove 7 and stopped orrestricted by the reflow stopper groove 7. Each gap between ends of thereflow stopper groove 7 and the step-like barrier wall 17 is so narrowas substantially restricting a further outward reflow of the resist mask48. An external shape or a circumferential shape of the reflow-deformedresist mask 48 provides a pattern shape. The external shape or acircumferential shape of the reflow-deformed resist mask 48 is definedby the step-like barrier wall 17 and outside edges of the reflow stoppergroove 7. The step-like barrier wall 17 and the reflow stopper groove 7enable a highly accurate control or definition to the pattern shape ofthe reflow-deformed resist mask 48. As long as the positions of thestep-like barrier wall 17 and the reflow stopper groove 7 are highlyaccurate, the pattern shape of the reflow-deformed resist mask 48 isalso highly accurate. Since the highly accurate positioning of thestep-like barrier wall 17 and the reflow stopper groove 7 is relativelyeasy by use of the known techniques, it is also relatively easy toobtain the desired highly accurate control or definition to the patternshape of the reflow-deformed resist mask 48.

[0158] With reference to FIGS. 8A and 8B, a second etching process iscarried out by use of the deformed resist mask 48 in combination withthe source and drain electrodes 13 and 14 as combined masks forselectively etching the amorphous silicon film 4, whereby the amorphoussilicon film 4 becomes an island layer 24 which has a pattern shapewhich is defined by the deformed resist mask 48 in combination with thesource and drain electrodes 13 and 14 as combined masks. The useddeformed resist mask 48 is then removed, whereby a thin film transistoris formed.

[0159] The island layer 24 of amorphous silicon underlies the ohmiccontact layers 10 and 11. The island layer 24 is thus electricallyconnected to the source and drain electrodes 13 and 14. A parasiticcapacitance between the gate electrode 2 and the source and drainelectrodes 13 and 14 depends on the pattern shape of the island layer24. Since it is possible to obtain a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 48 orthe pattern shape of the island layer 24, it is possible to obtain ahighly accurate control to the parasitic capacitance.

[0160] In the above described embodiment, the reflow of the residualresist film 38 is caused by exposing the residual resist film 38 to thesteam which contains the solution containing the organic solvent. Anyother know methods for causing the re-flow of the resist mask are, ofcourse, available. The re-flow may be caused by applying a heat to theresist mask.

[0161] The above novel method is further applicable to deformation toother pattern film than the resist mask, provided the pattern is allowedto be re-flowed by any available measures..

[0162] The above described novel method of the first embodiment may bemodified as follows. FIG. 9A is a fragmentary plan view of a thin filmtransistor of a third step involved in novel sequential fabricationprocesses in a first modification to the first embodiment in accordancewith the present invention. FIG. 9B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 9A, taken alongan A-A′ line.

[0163] The following descriptions will focus on the difference of thefirst modified method from the above novel method of the firstembodiment. In the above novel method of the first embodiment, the dummygate electrode 12 is separate from the gate electrode interconnection 2.In this first modified method, a dummy gate electrode 22 is connectedwith the gate electrode interconnection 2.

[0164] The dummy gate electrode 22 is generally U-shaped, so that thedummy gate electrode 22 surrounds the rectangle-shaped gate electrode 2.The dummy gate electrode 12 is separate from the gate electrode 2 butconnected with the gate electrode interconnection 2. One side of thegate electrode 2 is bounded with the gate electrode interconnection 2.The dummy gate electrode 22 extends along the remaining three sides ofthe gate electrode 2. An U-shaped gap is defined between inside edges ofthe dummy gate electrode 22 and the remaining three sides of the gateelectrode 2. The U-shaped gap has an uniform width and is formed betweenthe gate electrode 2 and the dummy gate electrode 22.

[0165] An upper surface of the top conductive film 6 also has a reflowstopper groove 27 which extends in a form of generally U-shape in planview. The reflow stopper groove 27 extends over the U-shaped groove inthe upper surface of the n+-type amorphous silicon film 5. The reflowstopper groove 27 is positioned indirectly over the U-shaped gap betweenthe gate electrode 2 and the dummy gate electrode 22.

[0166] In the re-flow process, a part of the re-flowed resist mask 58 isdropped into the channel region 15 and other parts of the re-flowedresist mask 58 are dropped into the reflow stopper groove 27 whichextends in a form of the generally U-shape and positioned indirectlyover the U-shaped gap between the gate electrode 2 and the dummy gateelectrode 22. An inward reflow of the resist mask 58 is dropped into thechannel region 15 and a further inward reflow of the resist mask 58 isrestricted by the channel region 15. An outward reflow of the resistmask 58 is omnidirectional. The outward reflow of the resist mask 58 inone direction toward a step-like barrier wall 17 which extendsindirectly over an edge of the gate electrode interconnection 2 isstopped or restricted by the step-like barrier wall 17. The remainingoutward reflow of the resist mask 58 in the remaining three directionstoward the reflow stopper groove 7 is dropped into the reflow stoppergroove 27 and stopped or restricted by the reflow stopper groove 27. Nogap is formed between ends of the reflow stopper groove 7 and thestep-like barrier wall 17, whereby complete restriction of a furtheroutward reflow of the resist mask 58 is obtained. An external shape or acircumferential shape of the reflow-deformed resist mask 58 provides apattern shape. The external shape or a circumferential shape of thereflow-deformed resist mask 58 is defined by the step-like barrier wall17 and outside edges of the reflow stopper groove 27. The step-likebarrier wall 17 and the reflow stopper groove 27 enable a highlyaccurate control or definition to the pattern shape of thereflow-deformed resist mask 58. As long as the positions of thestep-like barrier wall 17 and the reflow stopper groove 27 are highlyaccurate, the pattern shape of the reflow-deformed resist mask 58 isalso highly accurate. Since the highly accurate positioning of thestep-like barrier wall 17 and the reflow stopper groove 27 is relativelyeasy by use of the known techniques, it is also relatively easy toobtain the desired highly accurate control or definition to the patternshape of the reflow-deformed resist mask 58.

Second Embodiment

[0167] A second embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 10A is afragmentary plan view of a thin film transistor of a first step involvedin novel sequential fabrication processes in a second embodiment inaccordance with the present invention. FIG. 10B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 10A,taken along an A-A′ line. FIG. 11A is a fragmentary plan view of a thinfilm transistor of a second step involved in novel sequentialfabrication processes in a second embodiment in accordance with thepresent invention. FIG. 11B is a fragmentary cross sectional elevationview of a thin film transistor shown in FIG. 11A, taken along an A-A′line. FIG. 12A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in asecond embodiment in accordance with the present invention. FIG. 12B isa fragmentary cross sectional elevation view of a thin film transistorshown in FIG. 12A, taken along an A-A′ line. FIG. 13A is a fragmentaryplan view of a thin film transistor of a fourth step involved in novelsequential fabrication processes in a second embodiment in accordancewith the present invention. FIG. 13B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 13A, taken alongan A-A′ line. A thin film transistor is formed over an insulatingsubstrate 101.

[0168] With reference to FIGS. 10A and 10B, a bottom conductive film isformed over a top surface of the insulating substrate 101. The bottomconductive film is patterned to form a gate electrode interconnection102. The gate electrode interconnection 102 has a gate electrode 102which has a rectangle shape in plan view. The gate electrode 102 extendsfrom the gate electrode interconnection 102 in a direction perpendicularto a longitudinal direction of the gate electrode interconnection 102.

[0169] A gate insulating film 103 is formed over the insulatingsubstrate 101 and the gate electrode interconnection 102, and the gateelectrode 102. An amorphous silicon film 104 is formed over the uppersurface of the gate insulating film 103. An n+-type amorphous siliconfilm 105 is formed over the upper surface of the amorphous silicon film104.

[0170] The n+-type amorphous silicon film 105, the amorphous siliconfilm 104 and the gate insulating film 103 are selectively etched to forma trench groove 109 which extends in a form of generally U-shape in planview. A bottom of the trench groove 109 comprises a part of the topsurface of the insulating substrate 101. The trench groove 109 isgenerally U-shaped, so that the trench groove 109 surrounds therectangle-shaped gate electrode 102. The trench groove 109 is separatefrom the gate electrode 102 and from the gate electrode interconnection102. One side of the gate electrode 102 is bounded with the gateelectrode interconnection 102. The trench groove 109 extends along theremaining three sides of the gate electrode 102. The trench groove 109extends outside the gate electrode 102. The trench groove 109 has anuniform width.

[0171] With reference to FIGS. 11A and 11B, a conductive film 106 isentirely formed over the upper surface of the n+-type amorphous siliconfilm 105 and in the trench groove 109, wherein the bottom and side wallsof the trench groove 109 are covered by the conductive film 106, but thetrench groove 109 is not filled with the conductive film 106, whereby areflow stopper groove 107 is formed in the trench groove 109. Namely, anupper surface of the conductive film 106 also has a reflow stoppergroove 107 which extends in a form of generally U-shape in plan view.The reflow stopper groove 107 extends overlaps the U-shaped trenchgroove 109. The reflow stopper groove 107 is positioned along theU-shaped trench groove 109.

[0172] A resist mask 108 is selectively formed over the upper surface ofthe conductive film 106 by use of a lithography technique. The resistmask 8 comprises a thick resist mask 118 and a thin resist mask 128. Thethick resist mask 118 is positioned in selected regions adjacent to achannel region 115 which has a rectangle shape. The selected regionsalso have rectangle shape regions along opposite outsides of therectangle shape channel region 115. The thick resist mask 118 may have athickness of about 3 micrometers. The thin resist mask 128 may have athickness of about 0.2-0.7 micrometers.

[0173] A first etching process is carried out by use of the thick andthin resist masks 118 and 128 for selectively etching the conductivefilm 106 and the n+-type amorphous silicon film 105. The top conductivefilm 106 may comprise a metal film. The top conductive film 106 mayselectively be etched by a wet etching process to form source and drainelectrodes 113 and 114. The n+-type amorphous silicon film 105 may alsoselectively be etched by a dry etching process under a pressure of 10Pa, at a power of 1000W for 60 seconds, wherein source gas flow rateratios of SF₆/HCl/He are 100/100/150 sccm to form ohmic contact layers110 and 111 which underlie the source and drain electrodes 113 and 114,thereby making ohmic contacts between the amorphous silicon film 104 andthe source and drain electrodes 113 and 114.

[0174] Subsequently, a plasma ashing process is carried out in thepresence of plasma atmosphere with oxygen flow rate at 400 sccm under apressure of 20 Pa, and an RF power of 1000 W for 120 seconds. Thisplasma ashing process reduces the thickness of the resist mask 8,whereby the thin resist mask 128 is removed whilst the thick resist mask118 is reduced in thickness, whereby the thickness-reduced resist mask118 becomes a residual resist mask 138 which extends on the selectedregions adjacent to the channel region 115.

[0175] With reference to FIGS. 12A and 12B, the residual resist mask 138is then exposed to a steam of a solution which contains an organicsolvent at 27° C. for 1-3 minutes. This exposure process causes theorganic solvent to osmose into the residual resist mask 138, whereby theresidual resist mask 138 is dissolved and re-flowed, and the residualresist mask 138 becomes a reflow-deformed resist mask 148.

[0176] A part of the re-flowed resist mask 148 is dropped into thechannel region 115 and other parts of the re-flowed resist mask 148 aredropped into the reflow stopper groove 107 which extends in a form ofthe generally U-shape and positioned in the generally U-shaped trenchgroove 109. An inward reflow of the resist mask 148 is dropped into thechannel region 115 and a further inward reflow of the resist mask 148 isrestricted by the channel region 115. An outward reflow of the resistmask 148 is omnidirectional. The outward reflow of the resist mask 148in one direction toward a step-like barrier wall 117 which extendsindirectly over an edge of the gate electrode interconnection 102 isstopped or restricted by the step-like barrier wall 117. The remainingoutward reflow of the resist mask 148 in the remaining three directionstoward the reflow stopper groove 107 is dropped into the reflow stoppergroove 107 and stopped or restricted by the reflow stopper groove 107.Each gap between ends of the reflow stopper groove 107 and the step-likebarrier wall 117 is so narrow as substantially restricting a furtheroutward reflow of the resist mask 148. An external shape or acircumferential shape of the reflow-deformed resist mask 148 provides apattern shape. The external shape or a circumferential shape of thereflow-deformed resist mask 148 is defined by the step-like barrier wall117 and outside edges of the reflow stopper groove 107. The step-likebarrier wall 117 and the reflow stopper groove 107 enable a highlyaccurate control or definition to the pattern shape of thereflow-deformed resist mask 148. As long as the positions of thestep-like barrier wall 117 and the reflow stopper groove 107 are highlyaccurate, the pattern shape of the reflow-deformed resist mask 148 isalso highly accurate. Since the highly accurate positioning of thestep-like barrier wall 117 and the reflow stopper groove 107 isrelatively easy by use of the known techniques, it is also relativelyeasy to obtain the desired highly accurate control or definition to thepattern shape of the reflow-deformed resist mask 148.

[0177] With reference to FIGS. 13A and 13B, a second etching process iscarried out by use of the deformed resist mask 148 in combination withthe source and drain electrodes 113 and 114 as combined masks forselectively etching the amorphous silicon film 104, whereby theamorphous silicon film 104 becomes an island layer 124 which has apattern shape which is defined by the deformed resist mask 148 incombination with the source and drain electrodes 113 and 114 as combinedmasks. The used deformed resist mask 148 is then removed, whereby a thinfilm transistor is formed.

[0178] The island layer 124 of amorphous silicon underlies the ohmiccontact layers 110 and 111. The island layer 124 is thus electricallyconnected to the source and drain electrodes 113 and 114. A parasiticcapacitance between the gate electrode 102 and the source and drainelectrodes 113 and 114 depends on the pattern shape of the island layer124. Since it is possible to obtain a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 148or the pattern shape of the island layer 124, it is possible to obtain ahighly accurate control to the parasitic capacitance.

[0179] In the above described embodiment, the reflow of the residualresist film 138 is caused by exposing the residual resist film 138 tothe steam which contains the solution containing the organic solvent.Any other know methods for causing the re-flow of the resist mask are,of course, available. The re-flow may be caused by applying a heat tothe resist mask.

[0180] The above novel method is further applicable to deformation toother pattern film than the resist mask, provided the pattern is allowedto be re-flowed by any available measures..

[0181] The above described novel method of the second embodiment may bemodified as follows. FIG. 14A is a fragmentary plan view of a thin filmtransistor of a third step involved in novel sequential fabricationprocesses in a first modification to the second embodiment in accordancewith the present invention. FIG. 14B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 14A, taken alongan A-A′ line.

[0182] The following descriptions will focus on the difference of thefirst modified method from the above novel method of the secondembodiment. In the above novel method of the second embodiment, thetrench groove 109 is formed in generally U-shape, so that the trenchgroove 109 incompletely surrounds the gate electrode 102 in the threedirections other than one direction toward the gate electrodeinterconnection 102, in order to keep the trench groove 109 separatefrom the gate electrode interconnection 102. Further, the trench groove109 has a depth which is the same level as the top surface of theinsulating substrate 101. Namely, the bottom of the trench groove 109comprises a part of the top surface of the insulating substrate 101.

[0183] In accordance with this first modification to the above novelmethod of the second embodiment, a trench groove 129 is formed inrectangle annular shape in plan view, so that the trench groove 129completely surrounds the gate electrode 102 in all directions, withkeeping the trench groove 129 separate from the gate electrodeinterconnection 102, because the trench groove 129 has a shallower depthwhich is upper level than the top surface of the insulating substrate101. Namely, the bottom of the trench groove 109 has an intermediatelevel of the gate insulating film 103.

[0184] With reference to FIGS. 14A and 14B, the n+-type amorphoussilicon film 105, the amorphous silicon film 104 and the gate insulatingfilm 103 are selectively etched to form a trench groove 129 whichextends in a form of generally rectangle annular shape in plan view. Abottom of the trench groove 109 has an upper level than a top level ofthe gate electrode interconnection 102. The trench groove 129 isgenerally rectangle annular shaped, so that the trench groove 129surrounds the rectangle-shaped gate electrode 102 completely in alldirections. The trench groove 129 is separate from the gate electrode102 and from the gate electrode interconnection 102. The trench groove129 extends outside the gate electrode 102. The trench groove 129 has anuniform width.

[0185] An upper surface of the conductive film 106 also has a reflowstopper groove 127 which extends in a form of generally rectangleannular shape in plan view. The reflow stopper groove 127 extendsoverlaps the generally rectangle annular shaped trench groove 129. Thereflow stopper groove 127 is positioned along the generally rectangleannular shape trench groove 129.

[0186] In he re-flow process, a part of the re-flowed resist mask 158 isdropped into the channel region 115 and other parts of the re-flowedresist mask 158 are dropped into the reflow stopper groove 127 whichextends in a form of the generally rectangle annular shape andpositioned in the generally rectangle annular shape trench groove 129.An inward reflow of the resist mask 158 is dropped into the channelregion 115 and a further inward reflow of the resist mask 158 isrestricted by the channel region 115. An outward reflow of the resistmask 158 is omnidirectional. The outward reflow of the resist mask 158in one direction toward a step-like barrier wall 117 which extendsindirectly over an edge of the gate electrode interconnection 102 isstopped or restricted by the step-like barrier wall 117. The remainingoutward reflow of the resist mask 158 in the remaining three directionstoward the reflow stopper groove 127 is dropped into the reflow stoppergroove 127 and stopped or restricted by the reflow stopper groove 127.An external shape or a circumferential shape of the reflow-deformedresist mask 148 provides a pattern shape. The external shape or acircumferential shape of the reflow-deformed resist mask 158 is definedby the step-like barrier wall 117 and outside edges of the reflowstopper groove 127. The step-like barrier wall 117 and the reflowstopper groove 127 enable a highly accurate control or definition to thepattern shape of the reflow-deformed resist mask 158. As long as thepositions of the step-like barrier wall 117 and the reflow stoppergroove 127 are highly accurate, the pattern shape of the reflow-deformedresist mask 158 is also highly accurate. Since the highly accuratepositioning of the step-like barrier wall 117 and the reflow stoppergroove 127 is relatively easy by use of the known techniques, it is alsorelatively easy to obtain the desired highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 158.

Third Embodiment

[0187] A third embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 15A is afragmentary plan view of a thin film transistor of a first step involvedin novel sequential fabrication processes in a third embodiment inaccordance with the present invention. FIG. 15B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 15A,taken along an A-A′ line. FIG. 16A is a fragmentary plan view of a thinfilm transistor of a second step involved in novel sequentialfabrication processes in a third embodiment in accordance with thepresent invention. FIG. 16B is a fragmentary cross sectional elevationview of a thin film transistor shown in FIG. 16A, taken along an A-A′line. FIG. 17A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a thirdembodiment in accordance with the present invention. FIG. 17B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 17A, taken along a B-B′ line. A thin film transistor isformed over an insulating substrate 201.

[0188] With reference to FIGS. 15A and 15B, a bottom conductive film isformed over a top surface of the insulating substrate 201. The bottomconductive film is patterned to form a gate electrode interconnection202. The gate electrode interconnection 202 has a gate electrode 202which has a rectangle shape in plan view. The gate electrode 202 extendsfrom the gate electrode interconnection 202 in a direction perpendicularto a longitudinal direction of the gate electrode interconnection 202.

[0189] A gate insulating film 203 is formed over the insulatingsubstrate 201 and the gate electrode interconnection 202, and the gateelectrode 202. An amorphous silicon film 204 is formed over the uppersurface of the gate insulating film 203. An n+-type amorphous siliconfilm 205 is formed over the upper surface of the amorphous silicon film204. A conductive film 206 is entirely formed over the upper surface ofthe n+-type amorphous silicon film 205.

[0190] A resist mask 208 is selectively formed over the upper surface ofthe conductive film 206 by use of a lithography technique. The resistmask 208 comprises a thick resist mask 218 and a thin resist mask 228.The thick resist mask 218 is positioned in selected regions adjacent toa channel region 215 which has a rectangle shape. The selected regionsalso have rectangle shape regions along opposite outsides of therectangle shape channel region 215. The thick resist mask 218 may have athickness of about 3 micrometers. The thin resist mask 228 may have athickness of about 0.2-0.7 micrometers.

[0191] A first etching process is carried out by use of the thick andthin resist masks 218 and 228 for selectively etching the conductivefilm 206 and the n+-type amorphous silicon film 205. The top conductivefilm 206 may comprise a metal film. The top conductive film 206 mayselectively be etched by a wet etching process to form source and drainelectrodes 213 and 214. The n+-type amorphous silicon film 205 may alsoselectively be etched by a dry etching process under a pressure of 10Pa, at a power of 1000W for 60 seconds, wherein source gas flow rateratios of SF₆/HCl/He are 100/100/150 sccm.

[0192] As a result of this etching process, the n+-type amorphoussilicon film 205 and the conductive film 206 are patterned to form areflow stopper groove 207 which extends in a form of generally U-shapein plan view. Further, the n+-type amorphous silicon film 205 and thechannel region 215 are patterned. The patterned n+-type amorphoussilicon film 205 becomes ohmic contact layers 210 and 211. The patternedconductive film 206 becomes source and drain electrodes 213 and 214adjacent to the channel region 215 and also dummy source and drainelectrodes 233 and 234.

[0193] Each of the dummy source and drain electrodes 233 and 234 extendsin a form of generally L-shape in plan view, so that the paired dummysource and drain electrodes 233 and 234 extend in a form of generallyU-shape in plan view, provided that the paired dummy source and drainelectrodes 233 and 234 are separate from each other. In plan view, thepaired dummy source and drain electrodes 233 and 234 surround therectangle-shaped gate electrode 202 in three directions other than adirection toward the gate electrode interconnection 202. The paireddummy source and drain electrodes 233 and 234 are separated from thepaired source and drain electrodes 213 and 214 by the reflow stoppergroove 207. Accordingly, the paired dummy source and drain electrodes233 and 234 define outside edges of the reflow stopper groove 207, whilethe paired source and drain electrodes 213 and 214 define inside edgesof the reflow stopper groove 207. A bottom of the reflow stopper groove207 comprises a part of the upper surface of the amorphous silicon film204.

[0194] With reference to FIGS. 16A and 16B, a plasma ashing process iscarried out in the presence of plasma atmosphere with oxygen flow rateat 400 sccm under a pressure of 20 Pa, and an RF power of 1000 W for 120seconds. This plasma ashing process reduces the thickness of the resistmask 208, whereby the thin resist mask 228 is removed whilst the thickresist mask 218 is reduced in thickness, whereby the thickness-reducedresist mask 218 becomes a residual resist mask 238 which extends on theselected regions adjacent to the channel region 215.

[0195] With reference to FIGS. 17A and 17B, the residual resist mask 238is then exposed to a steam of a solution which contains an organicsolvent at 27° C. for 1-3 minutes. This exposure process causes theorganic solvent to osmose into the residual resist mask 238, whereby theresidual resist mask 238 is dissolved and re-flowed, and the residualresist mask 238 becomes a reflow-deformed resist mask 248.

[0196] A part of the re-flowed resist mask 248 is dropped into thechannel region 215 and other parts of the re-flowed resist mask 248 aredropped into the reflow stopper groove 207 which extends in a form ofthe generally U-shape and positioned in the generally U-shaped trenchgroove 109. An inward reflow of the resist mask 248 is dropped into thechannel region 215 and a further inward reflow of the resist mask 248 isrestricted by the channel region 215. An outward reflow of the resistmask 248 is omnidirectional. The outward reflow of the resist mask 248in one direction toward a step-like barrier wall 217 which extendsindirectly over an edge of the gate electrode interconnection 202 isstopped or restricted by the step-like barrier wall 217. The remainingoutward reflow of the resist mask 248 in the remaining three directionstoward the reflow stopper groove 207 is dropped into the reflow stoppergroove 207 and stopped or restricted by the reflow stopper groove 207. Agap between ends of the paired dummy source and drain electrodes 233 and234 is so narrow as substantially restricting a further outward reflowof the resist mask 248.

[0197] An external shape or a circumferential shape of thereflow-deformed resist mask 248 provides a pattern shape. The externalshape or a circumferential shape of the reflow-deformed resist mask 248is defined by the step-like barrier wall 217 and outside edges of thereflow stopper groove 207. The step-like barrier wall 217 and the reflowstopper groove 207 enable a highly accurate control or definition to thepattern shape of the reflow-deformed resist mask 248. As long as thepositions of the step-like barrier wall 217 and the reflow stoppergroove 207 are highly accurate, the pattern shape of the reflow-deformedresist mask 248 is also highly accurate. Since the highly accuratepositioning of the step-like barrier wall 217 and the reflow stoppergroove 207 is relatively easy by use of the known techniques, it is alsorelatively easy to obtain the desired highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 248.

[0198] A second etching process is carried out by use of the deformedresist mask 248 in combination with the source and drain electrodes 213and 214 as combined masks for selectively etching the amorphous siliconfilm 204, whereby the amorphous silicon film 204 becomes an island layer224 which has a pattern shape which is defined by the deformed resistmask 248 in combination with the source and drain electrodes 213 and 214as combined masks. The used deformed resist mask 248 is then removed,whereby a thin film transistor is formed.

[0199] The island layer 224 of amorphous silicon underlies the ohmiccontact layers 210 and 211. The island layer 224 is thus electricallyconnected to the source and drain electrodes 213 and 214. A parasiticcapacitance between the gate electrode 202 and the source and drainelectrodes 213 and 214 depends on the pattern shape of the island layer224. Since it is possible to obtain a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 248or the pattern shape of the island layer 124, it is possible to obtain ahighly accurate control to the parasitic capacitance.

[0200] In the above described embodiment, the reflow of the residualresist film 238 is caused by exposing the residual resist film 238 tothe steam which contains the solution containing the organic solvent.Any other know methods for causing the re-flow of the resist mask are,of course, available. The re-flow may be caused by applying a heat tothe resist mask.

[0201] The above novel method is further applicable to deformation toother pattern film than the resist mask, provided the pattern is allowedto be re-flowed by any available measures..

Fourth Embodiment

[0202] A fourth embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 18A is afragmentary plan view of a thin film transistor of a first step involvedin novel sequential fabrication processes in a fourth embodiment inaccordance with the present invention. FIG. 18B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 18A,taken along a C-C′ line. FIG. 19A is a fragmentary plan view of a thinfilm transistor of a second step involved in novel sequentialfabrication processes in a fourth embodiment in accordance with thepresent invention. FIG. 19B is a fragmentary cross sectional elevationview of a thin film transistor shown in FIG. 19A, taken along a C-C′line. FIG. 20A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in afourth embodiment in accordance with the present invention. FIG. 20B isa fragmentary cross sectional elevation view of a thin film transistorshown in FIG. 20A, taken along a C-C′ line. A thin film transistor isformed over an insulating substrate 201.

[0203] With reference to FIGS. 18A and 18B, a bottom conductive film isformed over a top surface of the insulating substrate 201. The bottomconductive film is patterned to form a gate electrode interconnection242 and a dummy gate electrode 252. The gate electrode interconnection242 has a gate electrode 242 which has a generally circular shape with aflat side in plan view. The flat side of the generally circular shapegate electrode 242 is adjacent to and separate from the dummy gateelectrode 252. The gate electrode 242 extends from the gate electrodeinterconnection 242 in a direction perpendicular to a longitudinaldirection of the gate electrode interconnection 242. The flat side ofthe generally circular shape gate electrode 242 is perpendicular to thelongitudinal direction of the gate electrode interconnection 242. Thedummy gate electrode 252 is generally I-shaped or rectangle-shape, sothat the dummy gate electrode 252 is adjacent to and separate from theflat side of the generally circular shape gate electrode 242.

[0204] The dummy gate electrode 252 is thus separate from the gateelectrode 242 and from the gate electrode interconnection 242. One sideof the generally circular shape gate electrode 242 is connected throughan extending part from the gate electrode interconnection 242, whereinthe extending part extends in perpendicular to the longitudinaldirection of the gate electrode interconnection 242. An I-shaped orrectangle-shaped gap is defined between the dummy gate electrode 252 andthe flat side of the generally circular shape gate electrode 242. TheI-shaped gap has an uniform width.

[0205] A gate insulating film 203 is formed over the insulatingsubstrate 201 and the gate electrode interconnection 242, the gateelectrode 242 and the dummy gate electrode 252, wherein the gateinsulating film 203 fills the I-shaped gap between the dummy gateelectrode 252 and the flat side of the generally circular shape gateelectrode 242. An upper surface of the gate insulating film 203 has agroove which extends in a form of generally I-shape in plan view. Thegroove extends over the I-shaped gap between the flat side of thegenerally circular shape gate electrode 242 and the dummy gate electrode252. The groove in the upper surface of the gate insulating film 203 isthus formed by the I-shaped gap between the flat side of the generallycircular shape gate electrode 242 and the dummy gate electrode 252.

[0206] An amorphous silicon film 204 is formed over the upper surface ofthe gate insulating film 203. An upper surface of the amorphous siliconfilm 204 also has a groove which extends in a form of generally I-shapein plan view. The groove extends over the I-shaped groove in the uppersurface of the gate insulating film 203.

[0207] An n+-type amorphous silicon film 205 is formed over the uppersurface of the amorphous silicon film 204. An upper surface of then+-type amorphous silicon film 205 also has a groove which extends in aform of generally I-shape in plan view. The groove extends over theI-shaped groove in the upper surface of the amorphous silicon film 204.

[0208] A top conductive film 206 is formed over the upper surface of then+-type amorphous silicon film 205. An upper surface of the topconductive film 206 also has a reflow stopper groove 247 which extendsin a form of generally I-shape in plan view. The reflow stopper groove247 extends over the I-shaped groove in the upper surface of the n+-typeamorphous silicon film 205. The reflow stopper groove 247 is positionedindirectly over the I-shaped gap between the flat side of the generallycircular shape gate electrode 242 and the dummy gate electrode 252.

[0209] A resist mask 208 is selectively formed over the upper surface ofthe top conductive film 206 by use of a lithography technique. Theresist mask 208 comprises a thick resist mask 258 and a thin resist mask268. The thick resist mask 258 is positioned in selected regionsadjacent to a channel region 255 which has a partial circle shape orC-shape. The selected regions also have rectangle shape regions alongopposite outsides of the rectangle shape channel region 255. The thickresist mask 258 may have a thickness of about 3 micrometers. The thinresist mask 268 may have a thickness of about 0.2-0.7 micrometers.

[0210] A first etching process is carried out by use of the thick andthin resist masks 18 and 28 for selectively etching the top conductivefilm 206 and the n+-type amorphous silicon film 205. The top conductivefilm 206 may comprise a metal film. The top conductive film 206 mayselectively be etched by a wet etching process to form source and drainelectrodes 253 and 254. The n+-type amorphous silicon film 205 may alsoselectively be etched by a dry etching process under a pressure of 10Pa, at a power of 1000W for 60 seconds, wherein source gas flow rateratios of SF₆/HCl/He are 100/100/150 sccm to form ohmic contact layers250 and 251 which underlie the source and drain electrodes 253 and 254,thereby making ohmic contacts between the amorphous silicon film 204 andthe source and drain electrodes 253 and 254. As a result, the channelregion 255, which has a partial circle shape or C-shape, is defined.

[0211] With reference to FIGS. 19A and 19B, a plasma ashing process iscarried out in the presence of plasma atmosphere with oxygen flow rateat 400 sccm under a pressure of 20 Pa, and an RF power of 1000 W for 120seconds. This plasma ashing process reduces the thickness of the resistmask 208, whereby the thin resist mask 268 is removed whilst the thickresist mask 258 is reduced in thickness, whereby the thickness-reducedresist mask 258 becomes a residual resist mask 278 which extends on theselected region which corresponds to a circular-shaped island portion ofthe drain electrode 254. The selected region, on which the residualresist mask 278 remains, is surrounded by the C-shaped or partiallycircle shaped channel region 255.

[0212] With reference to FIGS. 20A and 20B, the residual resist mask 278is then exposed to a steam of a solution which contains an organicsolvent. This exposure process causes the organic solvent to osmose intothe residual resist mask 278, whereby the residual resist mask 278 isdissolved and re-flowed, and the residual resist mask 278 becomes areflow-deformed resist mask 288.

[0213] A part of the re-flowed resist mask 288 is dropped into theC-shaped channel region 255 and other part of the re-flowed resist mask288 is dropped into the reflow stopper groove 247 which extends in aform of the generally I-shape and positioned indirectly over theI-shaped gap between the gate electrode 242 and the dummy gate electrode252. No inward reflow of the resist mask 288 is caused. An outwardreflow of the resist mask 288 is omnidirectional. The outward reflow ofthe resist mask 288 is dropped into the C-shaped channel region 255 andthe I-shaped reflow stopper groove 247 and stopped or restricted by thereflow stopper groove 247 and the C-shaped channel region 255. Anexternal shape or a circumferential shape of the reflow-deformed resistmask 48 provides a pattern shape. The external shape or acircumferential shape of the reflow-deformed resist mask 48 is almostdefined by the outside edge of the C-shaped channel region 255 and thereflow stopper groove 247. The outside edge of the C-shaped channelregion 255 and the reflow stopper groove 247 enable a highly accuratecontrol or definition to the pattern shape of the reflow-deformed resistmask 288. As long as the definitions of the outside edge of the C-shapedchannel region 255 and the reflow stopper groove 247 are highlyaccurate, the pattern shape of the reflow-deformed resist mask 288 isalso highly accurate. Since the highly accurate definitions of theoutside edge of the C-shaped channel region 255 and the reflow stoppergroove 247 are relatively easy by use of the known techniques, it isalso relatively easy to obtain the desired highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 288.

[0214] A second etching process is carried out by use of the deformedresist mask 288 in combination with the source and drain electrodes 253and 254 as combined masks for selectively etching the amorphous siliconfilm 204, whereby the amorphous silicon film 204 becomes an island layer264 which has a pattern shape which is defined by the deformed resistmask 288 in combination with the source and drain electrodes 253 and 254as combined masks. The used deformed resist mask 288 is then removed,whereby a thin film transistor is formed.

[0215] The island layer 264 of amorphous silicon underlies the ohmiccontact layers 250 and 251. The island layer 264 is thus electricallyconnected to the source and drain electrodes 253 and 254. A parasiticcapacitance between the gate electrode 242 and the source and drainelectrodes 253 and 254 depends on the pattern shape of the island layer264. Since it is possible to obtain a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 288or the pattern shape of the island layer 264, it is possible to obtain ahighly accurate control to the parasitic capacitance.

[0216] In the above described embodiment, the reflow of the residualresist film 278 is caused by exposing the residual resist film 278 tothe steam which contains the solution containing the organic solvent.Any other know methods for causing the re-flow of the resist mask are,of course, available. The re-flow may be caused by applying a heat tothe resist mask.

[0217] The above novel method is further applicable to deformation toother pattern film than the resist mask, provided the pattern is allowedto be re-flowed by any available measures..

[0218] In accordance with this novel method, the channel region 255, thesource electrode 253 are partially circle shape or C-shape. It is,however, possible to modify this shape into the rectangle, square andother polygonal shape, provided that the outward reflow of the resistfilm is restricted by the channel region and the reflow stopper groove.

Fifth Embodiment

[0219] A fifth embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 21A is afragmentary plan view of a thin film transistor of a first step involvedin novel sequential fabrication processes in a fifth embodiment inaccordance with the present invention. FIG. 21B is a fragmentary crosssectional elevation view of a thin film transistor shown in FIG. 21A,taken along an E-E′ line. FIG. 22A is a fragmentary plan view of a thinfilm transistor of a second step involved in novel sequentialfabrication processes in a fifth embodiment in accordance with thepresent invention. FIG. 22B is a fragmentary cross sectional elevationview of a thin film transistor shown in FIG. 22A, taken along an E-E′line. FIG. 23A is a fragmentary plan view of a thin film transistor of athird step involved in novel sequential fabrication processes in a fifthembodiment in accordance with the present invention. FIG. 23B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 23A, taken along an E-E′ line. FIG. 24A is a fragmentaryplan view of a thin film transistor of a fourth step involved in novelsequential fabrication processes in a fifth embodiment in accordancewith the present invention. FIG. 24B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 24A, taken alongan E-E′ line. A thin film transistor is formed over an insulatingsubstrate 401.

[0220] With reference to FIGS. 21A and 21B, a bottom conductive film isformed over a top surface of the insulating substrate 401. The bottomconductive film is patterned to form a gate electrode interconnection402. The gate electrode interconnection 402 has a gate electrode 402which has an octagonal shape in plan view. The gate electrode 402extends from the gate electrode interconnection 402 in a directionperpendicular to a longitudinal direction of the gate electrodeinterconnection 402.

[0221] A gate insulating film 403 is formed over the insulatingsubstrate 401 and the gate electrode interconnection 402, and the gateelectrode 402. An amorphous silicon film 404 is formed over the uppersurface of the gate insulating film 403. An n+-type amorphous siliconfilm 405 is formed over the upper surface of the amorphous silicon film404. A conductive film 406 is entirely formed over the upper surface ofthe n+-type amorphous silicon film 405.

[0222] A resist mask 408 is selectively formed over the upper surface ofthe conductive film 206 by use of a lithography technique. The resistmask 408 comprises a thick resist mask 458 and a thin resist mask 468.The thick resist mask 458 is positioned in a selected region which isover the octagonal shape gate electrode 402. The selected region is anoctagonal shape region. The thick resist mask 458 may have a thicknessof about 3 micrometers. The thin resist mask 468 may have a thickness ofabout 0.2-0.7 micrometers.

[0223] A first etching process is carried out by use of the thick andthin resist masks 458 and 468 for selectively etching the conductivefilm 406 and the n+-type amorphous silicon film 405. The top conductivefilm 406 may comprise a metal film. The top conductive film 406 mayselectively be etched by a wet etching process to form source and drainelectrodes 453 and 454. The n+-type amorphous silicon film 405 may alsoselectively be etched by a dry etching process under a pressure of 10Pa, at a power of 1000W for 60 seconds, wherein source gas flow rateratios of SF₆/HCl/He are 100/100/150 sccm.

[0224] As a result of this etching process, the n+-type amorphoussilicon film 405 and the conductive film 406 are patterned to form areflow stopper groove 407 which extends in a form of generally U-shapein plan view. Further, the n+-type amorphous silicon film 405 and thechannel region 455 are patterned. The patterned n+-type amorphoussilicon film 405 becomes ohmic contact layers 450 and 451. The patternedconductive film 406 becomes source and drain electrodes 453 and 454adjacent to the channel region 455.

[0225] The source electrode 453 extends in a form of combined modifiedT-shape and octagonal island shape. Namely, the source electrode 453includes an octagonal shape island portion and a modified T-shapedportion connected with the octagonal shape island portion. The octagonalshape island portion is surrounded by an octagonal shape annular channelregion 455. The drain electrode 454 includes an octagonal shape annularsurrounding portion which surrounds the octagonal shape island portionof the source electrode 453. The octagonal shape annular surroundingportion of the drain electrode 454 is separate by the octagonal shapeannular channel region 455 from the octagonal shape island portion ofthe source electrode 453. The octagonal shape annular surroundingportion of the drain electrode 454 has an opening side, so that theoctagonal shape annular surrounding portion incompletely surrounds theoctagonal shape island portion of the source electrode 453. The modifiedT-shaped portion of the source electrode 453 extends through the openingside to the octagonal shape island portion of the source electrode 453.The modified T-shaped portion of the source electrode 453 also extendsoutside the opening side of the octagonal shape annular surroundingportion of the drain electrode 454.

[0226] With reference to FIGS. 22A and 22B, a plasma ashing process iscarried out in the presence of plasma atmosphere with oxygen flow rateat 400 sccm under a pressure of 20 Pa, and an RF power of 1000 W for 120seconds. This plasma ashing process reduces the thickness of the resistmask 408, whereby the thin resist mask 468 is removed whilst the thickresist mask 458 is reduced in thickness, whereby the thickness-reducedresist mask 458 becomes a first residual resist mask 478 which extendson the octagonal shape island portion of the source electrode 453 and asecond residual resist mask 479 which extends on an inside peripheralregion of the octagonal shape annular surrounding portion of the drainelectrode 454.

[0227] With reference to FIGS. 23A and 23B, the residual resist masks478 and 479 are then exposed to a steam of a solution which contains anorganic solvent at 27° C. for 1-3 minutes. This exposure process causesthe organic solvent to osmose into the residual resist masks 478 and479, whereby the residual resist masks 478 and 479 are dissolved andre-flowed, and the residual resist masks 478 and 479 become areflow-deformed resist mask 488.

[0228] A part of the re-flowed resist mask 488 is dropped into thechannel region 455, and a part of the dropped re-flowed resist mask 488in the channel region 455 is further re-flowed out of the opening sideof the octagonal shape annular surrounding portion of the drainelectrode 454. This further outward re-flow from the opening side is,however, restricted by the modified T-shaped portion of the sourceelectrode 453. The reflow stopper groove 407, thus, comprises thechannel region 455 and a region between the opening side of theoctagonal shape annular surrounding portion of the drain electrode 454and the modified T-shaped portion of the source electrode 453.

[0229] As a modification, if a opening size of the opening side of theoctagonal shape annular surrounding portion of the drain electrode 454is too narrow as effectively restricting the further outward re-flow, itis possible to modify the T-shaped portion of the source electrode 453into an I-shape which connects with the octagonal shape island portionof the source electrode 453.

[0230] An external shape or a circumferential shape of thereflow-deformed resist mask 488 provides a pattern shape. The externalshape or a circumferential shape of the reflow-deformed resist mask 488is defined by the reflow stopper groove 407 including the channel region455. The reflow stopper groove 407 enable a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 488.As long as the reflow stopper groove 207 is highly accurate, the patternshape of the reflow-deformed resist mask 488 is also highly accurate.Since the highly accurate positioning of the reflow stopper groove 407is relatively easy by use of the known techniques, it is also relativelyeasy to obtain the desired highly accurate control or definition to thepattern shape of the reflow-deformed resist mask 488.

[0231] A second etching process is carried out by use of the deformedresist mask 488 in combination with the source and drain electrodes 453and 454 as combined masks for selectively etching the amorphous siliconfilm 404, whereby the amorphous silicon film 404 becomes an island layer464 which has a pattern shape which is defined by the deformed resistmask 488 in combination with the source and drain electrodes 453 and 454as combined masks.

[0232] The island layer 464 of amorphous silicon underlies the ohmiccontact layers 450 and 451. The island layer 464 is thus electricallyconnected to the source and drain electrodes 453 and 454. A parasiticcapacitance between the gate electrode 402 and the source and drainelectrodes 453 and 454 depends on the pattern shape of the island layer464. Since it is possible to obtain a highly accurate control ordefinition to the pattern shape of the reflow-deformed resist mask 488or the pattern shape of the island layer 464, it is possible to obtain ahighly accurate control to the parasitic capacitance.

[0233] With reference to FIGS. 24A and 24B, the used deformed resistmask 488 is then removed, whereby a thin film transistor is formed. Apassivation film 423 is formed. Contact holes 490 and 491 are formed inthe passivation film 423. A pixel electrode 492 and a gate terminalelectrode 493 are formed.

[0234] In the above described embodiment, the reflow of the residualresist masks is caused by exposing the residual resist masks to thesteam which contains the solution containing the organic solvent. Anyother know methods for causing the re-flow of the resist mask are, ofcourse, available. The re-flow may be caused by applying a heat to theresist mask.

[0235] The above novel method is further applicable to deformation toother pattern film than the resist mask, provided the pattern is allowedto be re-flowed by any available measures.

[0236] The above described novel method of the fifth embodiment may bemodified as follows. FIG. 25A is a fragmentary plan view of a thin filmtransistor of a third step involved in novel sequential fabricationprocesses in a first modification to the fifth embodiment in accordancewith the present invention. FIG. 25B is a fragmentary cross sectionalelevation view of a thin film transistor shown in FIG. 25A, taken alongan F-F′ line.

[0237] The following descriptions will focus on the difference of thefirst modified method from the above novel method of the fifthembodiment. In the above novel method of the fifth embodiment, the gateelectrode 402 and the gate electrode interconnection 402 have the samelevel and the same thickness. The re-flow stopper groove 407 alsocomprises the channel region 455 and the region between the opening sideto the octagonal shape island portion of the source electrode 453 andthe modified T-shaped portion of the source electrode 453. In this firstmodification, however, the octagonal shape gate electrode 402 isthickness-reduced except for an outside peripheral edge thereof. Theoutside peripheral edge of the octagonal shape gate electrode 402 havethe same thickness as the gate electrode interconnection 402. A step isformed at a boundary between the thickness reduced region and theoutside peripheral edge. This step of the gate electrode 402 causes astep of the modified T-shaped portion of the source electrode 453 and astep of the octagonal shape annular surrounding portion of the drainelectrode 454. The step of the modified T-shaped portion of the sourceelectrode 453 and the step of the octagonal shape annular surroundingportion of the drain electrode 454 serve as a reflow stopper wall. Inthis case, a peripheral edge of the reflow stopper groove 407 is definedby the step of the modified T-shaped portion of the source electrode 453and the step of the octagonal shape annular surrounding portion of thedrain electrode 454.

[0238] In this modification, the step of the modified T-shaped portionof the source electrode 453 and the step of the octagonal shape annularsurrounding portion of the drain electrode 454 are formed by thethickness-reduced portion of the gate electrode 402. It is alternativelypossible that a recessed portion is formed in the substrate 401, whereina step is formed on the peripheral edge of the recessed portion.

[0239] Alternatively, the above described novel method of the fifthembodiment may be modified as follows. FIG. 26A is a fragmentary planview of a thin film transistor of a third step involved in novelsequential fabrication processes in a second modification to the fifthembodiment in accordance with the present invention. FIG. 26B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 26A, taken along an F-F′ line.

[0240] The following descriptions will focus on the difference of thesecond modified method from the above novel method of the fifthembodiment. In the above novel method of the fifth embodiment, the gateelectrode 402 and the gate electrode interconnection 402 have the samelevel and the same thickness. The re-flow stopper groove 407 alsocomprises the channel region 455 and the region between the opening sideto the octagonal shape island portion of the source electrode 453 andthe modified T-shaped portion of the source electrode 453. In this firstmodification, however, the octagonal shape gate electrode 402 has athickness-reduced region 495. A step is formed at a peripheral edge ofthe thickness-reduced region 495. This step of the gate electrode 402causes a groove extending over the channel region 455 and the modifiedT-shaped portion of the source electrode 453. In this case, a peripheraledge of the reflow stopper groove 407 is defined by the channel region455 and the groove positioned over the thickness-reduced region 495 ofthe gate electrode 402.

[0241] In this modification, the groove is formed by thethickness-reduced region 495 of the gate electrode 402. It isalternatively possible that a recessed portion is formed in thesubstrate 401, wherein the groove is formed on the peripheral edge ofthe recessed portion.

[0242] Further, alternatively, the above described novel method of thefifth embodiment may be modified as follows. FIG. 27A is a fragmentaryplan view of a thin film transistor of a third step involved in novelsequential fabrication processes in a third modification to the fifthembodiment in accordance with the present invention. FIG. 27B is afragmentary cross sectional elevation view of a thin film transistorshown in FIG. 27A, taken along an F-F′ line.

[0243] The following descriptions will focus on the difference of thethird modified method from the above novel method of the fifthembodiment. The source electrode 453 extends in a form of octagonalisland shape. Namely, the source electrode 453 includes an octagonalshape island portion. The octagonal shape island portion is surroundedby an octagonal shape annular channel region 455. The drain electrode454 includes an octagonal shape annular surrounding portion whichsurrounds completely the octagonal shape island source electrode 453.The octagonal shape annular surrounding portion of the drain electrode454 is separate by the octagonal shape annular channel region 455 fromthe octagonal shape island source electrode 453. The octagonal shapeannular surrounding portion of the drain electrode 454 has no openingside, so that the octagonal shape annular surrounding portion completelysurrounds the octagonal shape island source electrode 453. In this case,the reflow stopper groove 407 extends on the channel region 455.

[0244] A passivation film 423 is formed. A contact hole 497 is formed inthe passivation film 423, so that the contact hole 497 is positionedover the octagonal shape island portion of the source electrode 453. Apixel electrode 496 is formed on the passivation film 423, wherein thepixel electrode 496 is connected through the contact hole 497 to theoctagonal shape island source electrode 453.

[0245] In the foregoing embodiments, the selected region, on which theresidual resist film remains, is preferably decided. The position of theselected region is optional, provided that the selected region ispositioned inside the reflow stopper groove, so that the outward reflowof the resist film is stopped or restricted by the reflow stopper grooveextending outside the resist film.

[0246] As modifications to the foregoing embodiments, the above re-flowstopper groove may be formed by forming a groove or a level-down regionon an upper surface of the substrate.

[0247] Although the invention has been described above in connectionwith several preferred embodiments therefor, it will be appreciated thatthose embodiments have been provided solely for illustrating theinvention, and not in a limiting sense. Numerous modifications andsubstitutions of equivalent materials and techniques will be readilyapparent to those skilled in the art after reading the presentapplication, and all such modifications and substitutions are expresslyunderstood to fall within the true scope and spirit of the appendedclaims.

What is claimed is:
 1. A method of deforming a pattern, said methodcomprising the steps of: forming, over a substrate, a layered-structurewith an upper surface including at least one selected region and atleast a re-flow stopper groove, wherein said re-flow stopper grooveextends outside said selected region and separate from said selectedregion; selectively forming at least one pattern on said selected regionand causing a re-flow of said pattern, wherein a part of an outwardlyre-flowed pattern is flowed into said re-flow stopper groove, and thenan outward re-flow of said pattern is restricted by said re-flow stoppergroove extending outside of said pattern, thereby to form a deformedpattern with at least an outside edge part defined by an outside edge ofsaid re-flow stopper groove.
 2. The method as claimed in claim 1,wherein said re-flow stopper groove excludes a channel region, and partsof said outwardly re-flowed pattern are flowed into both said re-flowstopper groove and said channel region.
 3. The method as claimed inclaim 2, wherein said re-flow stopper groove is separate from saidchannel region.
 4. The method as claimed in claim 3, wherein saidre-flow stopper groove is positioned indirectly over a gap between agate electrode and at least a dummy gate electrode.
 5. The method asclaimed in claim 3, wherein said re-flow stopper groove comprises arecessed trench groove formed in said layered-structure.
 6. The methodas claimed in claim 3, wherein said re-flow stopper groove comprises afirst gap between a source electrode and a dummy source electrode and asecond gap between a drain electrode and a dummy drain electrode.
 7. Themethod as claimed in claim 2, wherein said re-flow stopper groove isadjacent to said channel region.
 8. The method as claimed in claim 7,wherein said re-flow stopper groove is positioned indirectly over a gapbetween a gate electrode and at least a dummy gate electrode.
 9. Themethod as claimed in claim 7, wherein said re-flow stopper groove isdefined by both a side wall of an extending layer from one of source anddrain electrodes and a stepped portion of said channel region, wheresaid stepped portion is positioned indirectly over an edge of a gateelectrode.
 10. The method as claimed in claim 1, wherein said re-flowstopper groove includes a channel region, and a part of said outwardlyre-flowed pattern is flowed into said re-flow stopper groove.
 11. Themethod as claimed in claim 10, wherein said re-flow stopper groove andsaid channel region are in forms of annular shape, and an outsideperipheral edge of said re-flow stopper groove encompasses an outsideperipheral edge of said channel region, and said outside peripheral edgeof said re-flow stopper groove is defined by stepped portions of sourceand drain electrodes, where said stepped portions of said source anddrain electrodes are positioned indirectly over a stepped portion of agate electrode, and where said stepped portion of said gate electrodeextends in a form of annular shape and defines a depressed region ofsaid gate electrode.
 12. The method as claimed in claim 1, wherein saidre-flow stopper groove is included in a channel region which extendsoutside said selected region, and a part of said outwardly re-flowedpattern is flowed into said channel region.
 13. The method as claimed inclaim 12, wherein said re-flow stopper groove is positioned indirectlyover a groove of a gate electrode.
 14. The method as claimed in claim 1,wherein said re-flow stopper groove just overlaps a channel region whichextends outside said selected region, and a part of said outwardlyre-flowed pattern is flowed into said re-flow stopper groove.
 15. Themethod as claimed in claim 1, wherein said re-flow stopper groove andsaid channel region are an annular shaped region which is defined by anisland-shaped electrode and an annular-shaped electrode which surroundssaid island-shaped electrode completely.
 16. The method as claimed inclaim 1, wherein said re-flow stopper groove surrounds said selectedregion completely.
 17. The method as claimed in claim 1, wherein saidre-flow stopper groove surrounds said selected region incompletely. 18.The method as claimed in claim 1, wherein said selected region comprisesa set of plural selected regions separate from each other and adjacentto each other, and said re-flow stopper groove surrounds said set ofplural selected regions completely.
 19. The method as claimed in claim1, wherein said selected region comprises a set of plural selectedregions separate from each other and adjacent to each other, and saidre-flow stopper groove surrounds said set of plural selected regionsincompletely.
 20. The method as claimed in claim 1, wherein said patternis a pattern containing an organic material.
 21. The method as claimedin claim 20, wherein said pattern is a resist pattern.
 22. A method offorming a re-flowed pattern over a layered-structure, said methodcomprising the steps of: forming an original resist pattern over alayered-structure with an upper surface including at least one selectedregion and at least a re-flow stopper groove wherein extends outsidesaid selected region and separate from said selected region, and saidoriginal resist pattern comprising a thicker portion and a thinnerportion, and said thicker portion extending on a selected region,patterning a layered-structure by use of said original resist pattern;removing said thinner portion and reducing a thickness of said thickerportion to form a residual resist pattern unchanged in pattern shapefrom said thicker portion; and causing a re-flow of said residualpattern, wherein a part of an outwardly re-flowed pattern is flowed intosaid re-flow stopper groove, and then an outward re-flow of said patternis restricted by said re-flow stopper groove extending outside of saidpattern, thereby to form a deformed pattern with at least an outsideedge part defined by an outside edge of said re-flow stopper groove. 23.A method of patterning a layered-structure, said method comprising thesteps of: forming an original resist pattern over a layered-structurewith an upper surface including at least one selected region and atleast a re-flow stopper groove wherein extends outside said selectedregion and separate from said selected region, and said original resistpattern comprising a thicker portion and a thinner portion, and saidthicker portion extending on a selected region, patterning alayered-structure by use of said original resist pattern; removing saidthinner portion and reducing a thickness of said thicker portion to forma residual resist pattern unchanged in pattern shape from said thickerportion; and causing a re-flow of said residual pattern, wherein a partof an outwardly re-flowed pattern is flowed into said re-flow stoppergroove, and then an outward re-flow of said pattern is restricted bysaid re-flow stopper groove extending outside of said pattern, therebyto form a deformed pattern with at least an outside edge part defined byan outside edge of said re-flow stopper groove; and patterning saidlayered-structure by use of said deformed pattern.
 24. A semiconductordevice including gate, source and drain electrodes, a layered structureover a substrate, and said layered structure has a surface which furtherhas at least a groove, wherein said groove extends outside at least aselected region on said layered-structure, and said selected regionbeing adjacent to a channel region, and said groove extends outside ofsaid gate electrode, and said groove is separate by a gap from said gateelectrode.
 25. The semiconductor device as claimed in claim 24, whereinsaid groove surrounds said gate electrode incompletely.
 26. Thesemiconductor device as claimed in claim 24, wherein said groovesurrounds said gate electrode completely.
 27. The semiconductor deviceas claimed in claim 26, wherein said groove extends in an annular form.28. A semiconductor device including gate, source and drain electrodes,a layered structure over a substrate, and at least a groove formed insaid layered structure, wherein said groove extends outside at least aselected region on said layered-structure, and said selected regionbeing adjacent to a channel region, and said groove extends outside ofsaid gate electrode, and said groove is separate by a gap from said gateelectrode.
 29. The semiconductor device as claimed in claim 28, whereinsaid groove surrounds said gate electrode incompletely.
 30. Thesemiconductor device as claimed in claim 28, wherein said groovesurrounds said gate electrode completely.
 31. The semiconductor deviceas claimed in claim 30, wherein said groove extends in an annular form.32. A semiconductor device including a gate electrode and alayered-structure, wherein said gate electrode has at least a step, andan upper surface of said layered-structure also has at least a stepwhich is positioned over said step of said gate electrode.
 33. Thesemiconductor device as claimed in claim 32, wherein said gate has athickness-reduced region bounded by said step.
 34. A semiconductordevice including a gate electrode structure which further comprises atleast a gate electrode and at least a dummy gate electrode, wherein saiddummy gate electrode is separate by a gap from said gate electrode andpositioned outside of said gate electrode.
 35. The semiconductor deviceas claimed in claim 34, wherein said dummy gate electrode surrounds saidgate electrode incompletely.
 36. The semiconductor device as claimed inclaim 34, wherein said dummy gate electrode surrounds said gateelectrode completely.
 37. The semiconductor device as claimed in claim36, wherein said dummy gate electrode extends in an annular form. 38.The semiconductor device as claimed in claim 34, wherein said dummy gateelectrode extends adjacent to and parallel to a flat side of said gateelectrode.
 39. The semiconductor device as claimed in claim 34, whereinsaid semiconductor device further includes a multi-layer structurecomprising plural laminated layers which extend over said gate electrodestructure, and surfaces of said plural laminated layers have grooveswhich are positioned over said gap.
 40. A semiconductor device includinggate, source and drain electrodes, a layered structure over a substrate,and at least a groove in said layered structure, wherein said grooveextends outside at least a selected region on said layered-structure,and said selected region being adjacent to a channel region, and saidgroove extends outside of said gate electrode, and said groove isseparate by a gap from said gate electrode, and wherein at least a partof said source and drain electrodes is present in said groove.
 41. Thesemiconductor device as claimed in claim 40, wherein said groovesurrounds said gate electrode incompletely.
 42. The semiconductor deviceas claimed in claim 40, wherein said groove surrounds said gateelectrode completely.
 43. The semiconductor device as claimed in claim42, wherein said groove extends in an annular form.
 44. Thesemiconductor device as claimed in claim 40, wherein said groove extendsadjacent to and parallel to a flat side of said gate electrode.
 45. Asemiconductor device including gate, source and drain electrodes, dummysource and drain electrodes, a layered structure over a substrate, andat least a groove, wherein said dummy source and drain electrodes arepositioned outside said source and drain electrodes, and said grooveseparates said source and drain electrodes from said dummy source anddrain electrodes, and wherein said groove extends outside at least aselected region on said layered-structure, and said selected regionbeing adjacent to a channel region, and said groove extends outside ofsaid gate electrode in plan view, and said groove is separate from saidgate electrode in plan view.
 46. The semiconductor device as claimed inclaim 45, wherein said groove surrounds said gate electrodeincompletely.
 47. The semiconductor device as claimed in claim 45,wherein said groove surrounds said gate electrode completely.
 48. Thesemiconductor device as claimed in claim 47, wherein said groove extendsin an annular form.
 49. The semiconductor device as claimed in claim 45,wherein said groove extends adjacent to and parallel to a flat side ofsaid gate electrode.
 50. A semiconductor device including gate, sourceand drain electrodes, a channel region, and at least a groove, whereinfirst one of said source and drain electrodes includes an islandportion, and second one of said source and drain electrodes includes asurrounding portion which surrounds said channel region, and saidchannel region further surrounds said island portion, and saidsurrounding portion is separate by said channel region from said islandportion, and wherein said groove includes said channel region.
 51. Thesemiconductor device as claimed in claim 50, wherein said surroundingportion surrounds said island portion incompletely.
 52. Thesemiconductor device as claimed in claim 51, wherein said groove furtherincludes an additional groove which extends adjacent to an opening sideof said surrounding portion.
 53. The semiconductor device as claimed inclaim 52, further comprising a dummy gate electrode separate by a gapfrom said gate electrode, wherein said additional groove is positionedover said gap.
 54. The semiconductor device as claimed in claim 50,wherein said first one further includes a connecting portion, and anadditional extending portion which extends adjacent to an opening sideof said surrounding portion and which faces to said opening side, andsaid additional extending portion is connected through said connectingportion to said island portion.
 55. The semiconductor device as claimedin claim 54, wherein said connecting portion has a step-like wall. 56.The semiconductor device as claimed in claim 50, wherein saidsurrounding portion surrounds said island portion completely.
 57. Thesemiconductor device as claimed in claim 56, wherein said groove extendsin an annular form.
 58. A semiconductor device including alayered-structure over a substrate, wherein an upper surface of saidsubstrate has at least a groove, and an upper surface of saidlayered-structure also has at least a groove which is positioned oversaid groove of said substrate, and wherein said groove of said substrateselectively extends adjacent to a channel region.
 59. The semiconductordevice as claimed in claim 58, wherein said groove of said substrateextends around said channel region in plan view.
 60. The semiconductordevice as claimed in claim 59, wherein said groove of said substratesurrounds completely.
 61. The semiconductor device as claimed in claim59, wherein said groove of said substrate surrounds incompletely.
 62. Asemiconductor device including a layered-structure over a substrate,wherein an upper surface of said substrate has at least a level-downregion, and an upper surface of said layered-structure also has at leasta groove which extends over said level-down region of said substrate,and wherein said level-down region of said substrate selectively extendsincluding a channel region in plan view.